Bench Talk

Timing Parts Often Overlooked Compared to Rest of Design

(Source: Symmetry Electronics)

Clocks and oscillators run your components and ensure everything is operating systematically. Although timing parts are common and important, they are often overlooked in comparison to the rest of a design. When designing a clock tree, consider several factors when selecting an optimal timing solution. We’ll look at five common considerations for selecting a clock, based on your application’s form and function.

Free-running applications require independent clocks without any special phase-lock or synchronization requirements. Examples include standard processors, memory controllers, system on chips (SoCs), and peripheral components (such as USB, PCI Express switches).

Synchronous systems require continuous communication and network-level synchronization across all associated systems. In these applications, low-bandwidth phase-locked loop (PLL) based clocks provide jitter filtering to ensure that network-level synchronization is maintained. For example, synchronizing all serialization-deserialization (SerDes) reference clocks to a highly accurate network reference clock (such as Stratum 3 or GPS) guarantees synchronization across all system nodes. Examples of synchronous clock trees include Optical Transport Networking (OTN), synchronous optical networking and synchronous digital hierarchy (SONET/SDH), Mobile backhaul, Synchronous Ethernet, and HD Serial Digital Interface (HD SDI) video transmission.

What to consider: The type of clock you would use depends on whether the timing architecture is free-running or synchronous. If the architecture is free-running, a clock generator should be used. Conversely, a synchronous design requires a jitter-attenuating clock. Although synchronous systems do not need to have the same frequency, they need to have the same phase. 

Clock generators and clock buffers are useful when several reference frequencies are required, and the target ICs are either all on the same board or are in the same IC or field programmable gate array (FPGA).

The perceived challenge with clock generators is system layout. Placing a crystal adjacent to its target IC is simple and inexpensive. On the other hand, routing a clock signal from a clock generator to its target IC could be challenging despite its ability to cut costs. Implementing careful design and other techniques can ensure a centralized clock source delivers equal performance. Typically, if four or more clocks are required, designers can save money by utilizing a clock generator.

What to consider: When considering a clock generator, be sure to select one that is capable of outputting frequencies that are compatible with your design. Silicon Labs’ clock generators can be programmed using their ClockBuilder Pro Software to meet specific frequencies, outputs, and format requirements. Customers can custom order factory-programmed clock generator samples, typically with a two-week lead time.

Clock buffers distribute multiple copies or simple derivatives of an input/reference clock.

The reference clock can derive from a clock generator, XO, or system clock. Clock buffers scale their input clock from two to more than 10 outputs. They can include I²C, SPI, or pin-controlled features such as signal level and format translation, voltage level translation, multiplexing, and input frequency division. These features allow for space and cost savings by eliminating components, voltage dividers, and signal-level transition circuits.

What to consider: Consult Silicon Lab’s Timing Product Selector Guide to select a buffer that matches the number of outputs (or greater), output format, and jitter requirements of your design.

Jitter performance varies across a wide range of conditions, including:

• Device configuration
• Operation frequency
• Signal format
• Input clock slew rate and jitter
• Power supply and power supply noise

Jitter, defined as the deviation in time from an ideal reference clock in the time domain, is a critical specification of timing components. If not addressed, excessive clock jitter can compromise system performance. For an IC, jitter specifications will be given as a time-domain measurement, or more commonly in high-performance applications, as a frequency domain measurement in RMS Phase Jitter.

What to consider: The total clock tree jitter should be estimated to determine if there is sufficient system-level design margin before committing to a clock tree. A component with poor clock performance can compromise an entire system if the jitter is too high or poorly specified. It is fundamentally important to note that a clock tree’s jitter is not simply the sum of each component’s MAX specifications; it is the root of the sum of the squares of each device’s MAX RMS jitter.

Reference Silicon Labs’ Phase Noise to Jitter Calculator tool to easily identify clocks and oscillators that meet your jitter requirement.

Clocks and buffers come in an array of different formats, including:

• Fan-out: A term that defines the maximum number of digital inputs that the output of a single logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10 other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10.
• Low-Voltage Positive Emitter-Coupled Logic (LVPECL): A power-optimized version of Positive Emitter-Coupled Logic (PECL) uses a positive 3.3V power supply.
• Low-Voltage Differential Signaling (LVDS): Not just a physical layer specification, but a data link layer that is often added by communication standards and applications.
• Current Mode Logic (CML): Transmits data at speeds between 312.5Mbit/s and 3.125Gbit/s across standard circuit boards.
• High-Speed Current Steering Logic (HCSL): Differential logic with two output pins that switch between 0 and 14mA.
• Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS): The goal of an LVCMOS is to reduce the device geometry of integrated circuits reducing voltage operation.

What to consider: Utilize the format that corresponds with your design and associated requirements. Each of the above timing parts come in many different formats to support various design types.

As the leader in high-performance clocks and oscillators, Silicon Labs’ timing solutions offer the broadest portfolio of crystal oscillator, clock generator, clock buffer, and jitter attenuator families in the industry (Figure 1). Additionally, Silicon Labs offers the most frequency flexibility for clocks along with the industry’s lowest jitter. Before purchasing a clock, be sure to ask yourself the five questions outlined here to help narrow down the most optimal choice to support your design.

Figure 1: The Silicon Labs timing solution portfolio combines frequency flexibility with best-in-class jitter performance. (Source: Symmetry Electronics)

This post was written by Tyler Wojciechowicz and originally appeared on the Symmetry Electronics website.